An instruction requires five stages to execute:
- (a)An instruction requires five stages to execute: Stage Time Stage-1 (instruction fetch) 30 ns Stage-2 (instruction decode) 9 ns Stage-3 (instruction execute) 20 ns Stage-4 (Memory access) 35 ns Stage-5 (Store results) 10 ns An instruction must proceed through the stages in sequence. What is the minimum asynchronous time for any single instruction to complete?
- (b)Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a firstword (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. (i) What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. (ii) Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does this reduce the average memory access time?
- (c)(i) Compare the set of addressing modes of RISC and CISC machines. Give one example of addressing modes used in RISC and CISC respectively. (ii) Explain Parallel Processing, and also draw pipeline processing for instruction: Ai*Bi+Ci